SCHEDULES & PRICES

2022

Schedules 2022

GENERAL MPW & MINI@SIC SCHEDULES - 2022

Here you can find General MPW and mini@sic run schedules and pricelists for 2022.

To reserve your seat on a run, please register your design in the Registration Form or contact the EUROPRACTICE partner responsible for the technology.

PRICELISTS - 2022

There are two prices in the EUROPRACTICE lists: Discounted and Standard.

DISCOUNTED PRICE

Three conditions should be met for Discounted prices:

Customer is an academic institution or a research facility from one of the 28 EU countries together with Albania, Armenia, Azerbaijan, Belarus, Bosnia-Herzegovina, Georgia, Iceland, Israel, Liechtenstein, North Macedonia, Moldova, Montenegro, Norway, Switzerland, Turkey, Serbia and Ukraine.
Customer is a registered EUROPRACTICE member who has paid the Full-IC annual membership fee.
The intended design will be done for educational purposes or for publicly funded research.

STANDARD PRICE

Standard prices apply to all other customers.

ams MPW	Feb	May	Jun	Sep	Oct	Nov
ams 0.35µ CMOS C35B4C3 4M/2P/HR/5V IO	21		27		24
ams 0.35µ CMOS C35OPTO 4M/2P/5V IO	21		27		24
ams 0.35µ HV CMOS H35B4D3 120V 4M		2				7
ams 0.35µ SiGe-BiCMOS S35D4M5 / CMOS-RF C35B4M3 4M/4P Thick MET4 – MIM	7			26

Important notes: Dates are GDS submission deadlines. Design registration must be done at least 2 weeks in advance.

Dates in red are MPW runs on request.

ams MPW Pricelist	Standard EUR / mm²	Discounted EUR / mm²
ams 0.35µ CMOS C35B4C3 4M/2P/HR/5V IO	640¹	580¹
ams 0.35µ CMOS C35OPTO 4M/2P/5V	800²	700²
ams 0.35µ HV CMOS H35B4D3 120V 4M	880¹	800¹
ams 0.35µ SiGe-BiCMOS S35D4M5 /CMOS-RF C35B4M3 4M/4P Thick MET4 – MIM	880¹	800¹

Important notes:

¹ Price = area (mm²) * price/mm² with min. fabrication cost equivalent to 7mm²

²Price = area (mm²) * price/mm²with min. fabrication cost equivalent to 20mm²

GLOBALFOUNDRIES MPW	Jan	Feb	Mar	Apr	May	Jun	Jul	Aug	Sep	Nov	Dec
GLOBALFOUNDRIES SiGe 8XP		21			23			22		21
GLOBALFOUNDRIES 130nm BCDlite – Gen2			21					29
GLOBALFOUNDRIES 55 nm LPe-RF						20
GLOBALFOUNDRIES 45RFSOI	3				16				19
GLOBALFOUNDRIES 45nm SPCLO – Silicon Photonics			14			13			12		12
GLOBALFOUNDRIES 28 nm SLPe					9			8
GLOBALFOUNDRIES 22 nm FDSOI	10		7		2		4		5	1
GLOBALFOUNDRIES 12 nm LP+	10			11	11				7

Important notes: Dates are Registration deadlines after which designs cannot be accepted.

Final GDSII file must be submitted within 6 weeks after this date.

Dates in red are preliminary.

A cancellation fee is applicable if the registration is cancelled later than 2 weeks after the Registration deadline or if the customer is unable to provide a DRC-clean GDS before the Tapeout deadline.

GLOBALFOUNDRIES MPW Pricelist	Standard EUR / mm²	Discounted EUR / mm²
GLOBALFOUNDRIES SiGe 8XP	4,700 ¹	4,500 ¹
GLOBALFOUNDRIES 130 nm BCDlite	1,900 ²	1,800 ²
GLOBALFOUNDRIES 55 nm BCDlite	5,500 ¹	5,200 ¹
GLOBALFOUNDRIES 45RFE	10,200 ¹	9,800¹
GLOBALFOUNDRIES 45nm SPCLO -Silicon Photonics (price per fixed block 5mm x 5mm)	231,000	220,000
GLOBALFOUNDRIES 28 nm SLPe	12,100 ³	11,500 ³
GLOBALFOUNDRIES 22 nm FDSOI	17,900 ³	17,000 ³
GLOBALFOUNDRIES 12 nm LP+	29,400 ³	28,000 ³

Important notes:

¹ Price = area (mm²) * price/mm² with min. fabrication cost equivalent to 12 mm². Any edge length between 1.0 mm to 11 mm is possible.

The mentioned die size is referred to the Pre-Shrink die size.

² Price = area (mm²) * price/mm² with min. fabrication cost equivalent to 25 mm². Any edge length between 1.0 mm to 11 mm is possible.

The mentioned die size is referred to the Pre-Shrink die size.

³ Price = area (mm²) * price/mm² with min. fabrication cost equivalent to 9 mm². Any edge length between 1.0 mm to 11 mm is possible.

The mentioned die size is referred to the Pre-Shrink die size.

GLOBALFOUNDRIES mini@sic	Jan	Mar	Apr	May	Jun	Jul	Aug	Sep	Nov	Dec
GLOBALFOUNDRIES SiGe 8XP				23			22		21
GLOBALFOUNDRIES 130nm BCDlite – Gen2		21					29
GLOBALFOUNDRIES 55 nm LPe-RF					20
GLOBALFOUNDRIES 45RFSOI				16				19
GLOBALFOUNDRIES 45nm SPCLO – Silicon Photonics								12		12
GLOBALFOUNDRIES 28 nm SLPe							8
GLOBALFOUNDRIES 22 nm FDSOI	10	7		2		4		5	1
GLOBALFOUNDRIES 12 nm LP+			11	11				7

Important notes: The mini@sic model of GLOBALFOUNDRIES is available only for Universities and Research Institutions.

Dates are Registration deadlines after which designs cannot be accepted.

Final GDSII file must be submitted within 6 weeks after this date.

Dates in red are preliminary.

GLOBALFOUNDRIES mini@sic Pricelist	Standard EUR / mm²	Discounted EUR / mm²
GLOBALFOUNDRIES SiGe 8XP	7,400 ¹	7,000 ¹
GLOBALFOUNDRIES 130nm BCDlite – Gen2	3,200 ²	3,000 ²
GLOBALFOUNDRIES 55 nm BCDlite	8,100 ¹	7,700 ¹
GLOBALFOUNDRIES 45RFE	12,800³	12,200 ³
GLOBALFOUNDRIES 45nm SPCLO -Silicon Photonics	147,000 ⁴	140,000 ⁴
GLOBALFOUNDRIES 28 nm SLPe	16,700 ³	15,900 ³
GLOBALFOUNDRIES 22 nm FDSOI	23,600 ³	22,500 ³
GLOBALFOUNDRIES 12 nm LP+	36,800 ³	35,000 ³

Important notes:

¹ Price = area (mm²) * price/mm² with min. fabrication cost equivalent to 2 mm². The mentioned die size is referred to the Pre-Shrink die size.

² Price = area (mm²) * price/mm² with min. fabrication cost equivalent to 4 mm². The mentioned die size is referred to the Pre-Shrink die size.

³ Price = area (mm²) * price/mm² with min. fabrication cost equivalent to 1 mm².The mentioned die size is referred to the Pre-Shrink die size.

⁴ Price = fixed block size of 5mm x 2.455mm or 2.455mm x 5mm.

Fraunhofer IISB		Jan	Feb	Mar	Apr	May	Jun	Jul	Aug	Sep	Oct	Nov	Dec
4H-SiC CMOS HIGH TEMPERATURE												28

Important notes: Dates are GDS submission deadlines. Design registration must be done at least 4 weeks in advance.

Fraunhofer IISB Pricelist		Standard EUR / mm²	Discounted EUR / mm²
4H-SiC CMOS HIGH TEMPERATURE		825	750

Important notes: Price = area (mm²) * price/mm² with min. fabrication cost equivalent to 4 mm²

IHP MPW	Feb	Mar	Jul	Sep	Oct	Nov
IHP SGB25V 0.25µ SiGe:C Bipolar/Analog, Ft/Fmax= 75/95GHz, 5M/MIM, breakdown voltages up to 7V		18	15
IHP SG25H3 0.25µ SiGe:C Bipolar/Analog, Ft/Fmax= 110/180GHz, 5M/MIM, breakdown voltages up to 7V		18	15
SG25H5_EPIC Bipolar/Analog, Ft/Fmax= 220/290GHz, 7M/MIM + Photonics		18			21
IHP SG13S SiGe:C Bipolar/Analog, Ft/Fmax= 250/340GHz, 7M/MIM + optional TSV			1	2		25
IHP SG13C SiGe:C CMOS 7M/MIM			1	2		25
IHP SG13G2 SiGe:C Bipolar/Analog, Ft/Fmax= 350/450GHz, 7M/MIM + optional TSV			1	2		25
IHP SG13G2Cu FEOL process SG13G2 together with Cu BEOL option	4		1 *	2		25
IHP SG13SCu FEOL process SG13S together with Cu BEOL option	4		1 *	2		25
IHP SG13S + MEMRES Module			1			25
IHP SG25 PIC (Photonics, Ge Photo-diode, BEOL)			29
IHP BEOL SG13 (M1 and Metal Layers Above) + optional LBE or TSV	25

Important notes: Dates are Registration deadlines. Final GDSII file must be submitted within 10 days after this date.

* Additional MPW runs offered only when the cumulative area > 10 mm².

MEMRES is available for the IHP SG13S technology with extra charge.

TSV is available for IHP SG13S and SG13G2 technologies with extra charge

Cu Pillar and Bumping are available for all IHP technologies with extra charge

Local Backside Etching (LBE) is not offered for EPIC runs and runs with Cu-BEOL

IHP MPW Pricelist	Standard EUR / mm²	Discounted EUR / mm²
IHP SGB25V 0.25μ SiGe:C Bipolar/Analog, Ft/Fmax= 75/95GHz, 5M/MIM, breakdown voltages up to 7V	2,500 ¹	2,125 ¹
IHP SG25H3 0.25μ SiGe:C Bipolar/Analog, Ft/Fmax= 110/180GHz, 5M/MIM, breakdown voltages up to 7V	3,800 ¹	3,230 ¹
SG25H5_EPIC Bipolar/Analog, Ft/Fmax= 220/290GHz, 7M/MIM + Photonics	8,000 ¹	6,800 ¹
IHP SG25 PIC (Photonics, Ge Photo-diode, BEOL)	3,800 ¹	3,230 ¹
IHP SG13S SiGe:C Bipolar/Analog, Ft/Fmax= 250/340GHz, 7M/MIM + optional TSV	6,300 ¹	5,355 ¹
IHP SG13C SiGe:C CMOS 7M/MIM	4,500 ¹	3,825 ¹
IHP SG13G2 SiGe:C Bipolar/Analog, Ft/Fmax= 350/450GHz, 7M/MIM + optional TSV	7,300 ¹	6,205 ¹
IHP SG13G2Cu FEOL process SG13G2 together with Cu BEOL option	7,000 ¹	5,950 ¹
IHP SG13SCu FEOL process SG13S together with Cu BEOL option	6,100 ¹	5,185 ¹
IHP BEOL SG13 (M1 and Metal Layers Above) + optional LBE or TSV	1,000 ¹	850 ¹
IHP Special Services
Bumping (available for all IHP technologies)	6,500²	6,500 ²
Localized Back side Etching (available for all IHP technologies) not offered for EPIC/PIC runs	5,000²	4,250 ²
TSV to ground (SG13)	7,500 ²	6,375 ²
Cu Pillar	18,500²	on request
IHP SG13S + MEMRES Modul on time fee	2,500²	2,000²
IHP SG13S + MEMRES Modul additional fee per mm²	600¹	510¹

Important notes:

¹ Price = area (mm²) * price/mm² with min. fabrication cost equivalent to 0.8mm².
The chip area is inclusive of the filler cells outside the seal ring.
² One-off fee

IHP MPW	Feb	Mar	Jul	Sep	Oct	Nov
IHP SGB25V 0.25µ SiGe:C Bipolar/Analog, Ft/Fmax= 75/95GHz, 5M/MIM, breakdown voltages up to 7V		18	15
IHP SG25H3 0.25µ SiGe:C Bipolar/Analog, Ft/Fmax= 110/180GHz, 5M/MIM, breakdown voltages up to 7V		18	15
SG25H5_EPIC Bipolar/Analog, Ft/Fmax= 220/290GHz, 7M/MIM + Photonics		18			21
IHP SG13S SiGe:C Bipolar/Analog, Ft/Fmax= 250/340GHz, 7M/MIM + optional TSV			1	2		25
IHP SG13C SiGe:C CMOS 7M/MIM			1	2		25
IHP SG13G2 SiGe:C Bipolar/Analog, Ft/Fmax= 350/450GHz, 7M/MIM + optional TSV			1	2		25
IHP SG13G2Cu FEOL process SG13G2 together with Cu BEOL option	4		1 *	2		25
IHP SG13SCu FEOL process SG13S together with Cu BEOL option	4		1 *	2		25
IHP SG13S + MEMRES Module			1			25
IHP SG25 PIC (Photonics, Ge Photo-diode, BEOL)			29
IHP BEOL SG13 (M1 and Metal Layers Above) + optional LBE or TSV	25

Important notes: Dates are Registration deadlines. Final GDSII file must be submitted within 10 days after this date.

* Additional MPW runs offered only when the cumulative area > 10 mm².

MEMRES is available for the IHP SG13S technology with extra charge.

TSV is available for IHP SG13S and SG13G2 technologies with extra charge

Cu Pillar and Bumping are available for all IHP technologies with extra charge

Local Backside Etching (LBE) is not offered for EPIC runs and runs with Cu-BEOL

IHP MPW Pricelist	Standard EUR / mm²	Discounted EUR / mm²
IHP SGB25V 0.25μ SiGe:C Bipolar/Analog, Ft/Fmax= 75/95GHz, 5M/MIM, breakdown voltages up to 7V	2,125 ¹	2,000 ¹
IHP SG25H3 0.25μ SiGe:C Bipolar/Analog, Ft/Fmax= 110/180GHz, 5M/MIM, breakdown voltages up to 7V	3,230 ¹	3,040 ¹
SG25H5_EPIC Bipolar/Analog, Ft/Fmax= 220/290GHz, 7M/MIM + Photonics	6,800 ¹	6,000 ¹
IHP SG25 PIC (Photonics, Ge Photo-diode, BEOL)	3,230 ¹	2,660 ¹
IHP SG13S SiGe:C Bipolar/Analog, Ft/Fmax= 250/340GHz, 7M/MIM + optional TSV	5,355 ¹	4,410 ¹
IHP SG13C SiGe:C CMOS 7M/MIM	3,825 ¹	3,600 ¹
IHP SG13G2 SiGe:C Bipolar/Analog, Ft/Fmax= 350/450GHz, 7M/MIM + optional TSV	6,205 ¹	5,110 ¹
IHP SG13G2Cu FEOL process SG13G2 together with Cu BEOL option	5,950 ¹	5,000 ¹
IHP SG13SCu FEOL process SG13S together with Cu BEOL option	5,185 ¹	4,360 ¹
IHP BEOL SG13 (M1 and Metal Layers Above) + optional LBE or TSV	850 ¹	800 ¹
IHP Special Services
Bumping (available for all IHP technologies)	6,500²	4,700 ²
Localized Back side Etching (available for all IHP technologies) not offered for EPIC/PIC runs	4,250²	2,500 ²
TSV to ground (SG13)	6,375 ²	4,500 ²
Cu Pillar	on request	on request
IHP SG13S + MEMRES Modul on time fee	2,000²	2,000²
IHP SG13S + MEMRES Modul additional fee per mm²	510¹	450¹

Important notes:

¹ Price = area (mm²) * price/mm² with min. fabrication cost equivalent to 0.8mm².
The chip area is inclusive of the filler cells outside the seal ring.
² One-off fee

Standard mini@sic price is meant for designs created for educational purposes or publicly funded research for non-EU countries.

Discounted mini@sic price is meant for designs created for educational purposes or publicly funded research for the EU countries.

TSMC MPW	Jan	Feb	Mar	Apr	May	Jun	Jul	Aug	Sep	Oct	Nov	Dec
TSMC 0.18µm CMOS Logic or Mixed-Signal/RF, General Purpose	5	23	30	6 13 27		1 8 22 29	20	3 24 31
TSMC 0.18µm CMOS High Voltage BCD Gen 2	5		2	27	4	1 8 22 29		3 24
TSMC 0.13µm CMOS Logic or MS/RF, GP or LP (8-inch)			9		4
TSMC 0.13µm CMOS BCD plus (12-inch)							20				9
TSMC 0.13µm CMOS Logic or MS/RF, GP or LP (12-inch)	5	9	30			8	20				9
TSMC 90nm CMOS Logic or MS/RF, GP or LP			9		11			10				7
TSMC 65nm CMOS Logic or MS/RF, GP or LP			2	13		1	27	31		26		21
TSMC 40nm CMOS Logic or MS/RF, GP or LP (no triple gate oxide)		2 23	30			8	27	31		5	23
TSMC 28nm CMOS Logic or RF HPC/HPC+		23		27			6		7		30	14
TSMC 16nm CMOS Logic or RF FinFET Compact		2		6	25		27		21		23

Important notes:

Dates are GDS submission deadlines.

Several TSMC shuttles are extremely loaded. For any technology, please make your design registration as early as possible. We will work with you and do our best to get your design on the run. If required, a waiting list will be created.

Bumping is available upon request for all 12-inch technologies.

Contact eptsmc@imec.be if any of the following options are used: Bumping, MTP/OTP, Deep Trench, High Linearity MiM, Schottky Barrier Diode, ULL N/PMOS.

Prices for TSMC technologies can be calculated through the online Price Request Form:

Exceptionally, prices for the TSMC University FinFET Program can be found here:

When 4 or more independent sub-designs are registered in one MPW submission to optimise the minimum charged area, an additional verification charge of 1,000 USD is applicable. This is regardless of the request and charges for sub die sawing (6 USD per additional die obtained from the base MPW submission).

TSMC mini@sic	Feb	Apr	May	Jun	Jul	Aug	Sep	Oct	Nov
TSMC 0.18µm CMOS General Mixed-Signal/RF	23 *		18			31
TSMC 0.18µm CMOS High Voltage BCD Gen 2		6				24
TSMC 65nm CMOS Low Power MS/RF	2	20		15			14		23**
TSMC 40nm CMOS Low Power MS/RF		27						19
TSMC 28nm CMOS RF HPC+	2		25		27			26
TSMC 16nm CMOS RF FinFET Compact									16

Important notes:

Dates are GDS submission deadlines.

Bumping is available upon request for all 12-inch technologies.

Contact eptsmc@imec.be if any of the following options are used: Bumping, MTP/OTP, Deep Trench, High Linearity MiM, Schottky Barrier Diode, ULL N/PMOS.

* no ULL N/PMOS available

** This run is full. No registrations are possible.

Please check additional technology options for TSMC mini@sic:

TSMC mini@sic Pricelist	Standard prices		Discounted prices
	EUR / min area	EUR / extra area	EUR / min area	EUR / extra area
TSMC 0.18 MS RF (min area = 3 mm²)	3,140	909 / 1 mm²	2,720	864 / 1 mm²
TSMC 0.18 BCD Gen II (min area = 4 mm²)	4,725	1,025 / 1 mm²	4,085	975 / 1 mm²
TSMC 65 LP MS RF (min area = 1 mm²)	4,032	336 / 0.1 mm²	3,371	320 / 0.1 mm²
TSMC 40 LP MS RF (min area = 3 mm²) *	16,665	531 / 0.1 mm²	15,832	504 / 0.1 mm²
TSMC 28 HPC+ RF (min area = 1 mm²) *	9,755	717 / 0.1 mm²	7,833	681 / 0.1 mm²

Important notes:

The prices are area based, and the aspect ratio is free to choose but it is strongly recommended not to have sides less than 1mm.
Subdicing is not supported on mini@sic.
Design registration must be done at least 3 months in advance, preferably at the moment of reservation.
* The areas in the table for 28nm and 40nm are on-silicon dimensions. This means the designed area can be (area/0.81).

Please check additional technology options for TSMC mini@sic:

UMC MPW	Jan	Feb	Mar	Apr	May	Jun	Jul	Aug	Sep	Oct	Nov	Dec
UMC 28N Logic/Mixed-Mode – HPC		7			9			8			7
UMC 40N Logic/Mixed-Mode – LP		14	14				11		5		21
UMC 65N Logic/Mixed-Mode/RF – LL	3		7		16		18			31		5
UMC 55N Logic/Mixed-Mode/RF – SP	3		7		16		18			31		5
UMC L110AE Logic/Mixed-Mode/RF		28		25		27		22		24		5
UMC L130 Logic				25						24
UMC L130 Mixed-Mode/RF				25						24
UMC L180 Logic GII	31				2			1		31
UMC L180 Mixed-Mode/RF	31				2			1		31

Important notes: Dates are GDS submission deadlines. Design registration must be done at least 3 weeks in advance.

Additional technology options are available:

UMC MPW Pricelist	Standard EUR / block	Discounted EUR / block
UMC L180 Logic GII, Mixed-Mode/RF	16,560 ¹	15,732 ¹
UMC L180 EFLASH Logic GII	21,045 ¹	20,010 ¹
UMC L130 Logic/Mixed-Mode/RF	27,600 ¹	26,220 ¹
UMC L110AE Logic/Mixed-Mode/RF	30,418 ¹	28,911 ¹
UMC L65nm Logic, Mixed-Mode/ RF – LL/SP	43,700 ²	41,515 ²
UMC 55N Logic/Mixed-Mode/RF – SP	45,425 ²	43,171 ²
UMC 40N Logic/Mixed-Mode – LP	84,698 ²	80,477 ²
UMC 28N Logic/ Mixed-Mode – HPC	On request. Please, contact epumc@imec.be

Important notes:

¹ Price = per block of 5mm x 5mm needed to fit the design in.
² Price = per block of 4mm x 4mm needed to fit the design in.

UMC mini@sic	Jan	Feb	Apr	Jul	Aug	Oct	Nov	Dec
UMC 65N Logic/Mixed-Mode/RF – LL		28		11				5
UMC L110AE Mixed-Mode/RF			18		15		28
UMC L180 Mixed-Mode/RF	24		25	25		24

Important notes: Dates are GDS submission deadlines. Design registration must be done at least 3 weeks in advance.

Additional technology options are available:

UMC mini@sic Pricelist	Standard EUR / block	Discounted EUR / block
UMC L180 Mixed-Mode/RF – 1P6M – 1.8V/3.3V *	3,588 ¹	3,002 ¹
UMC L110AE Logic/Mixed-Mode/RF **	8,913 ²	8,062 ²
UMC L65N Logic/Mixed-Mode LL ***	11,328 ³	10,649 ³

Important notes:

¹ Price = per block of 1525μm x 1525μm needed to fit the design in. Adding two blocks together to one block is possible.

² Price = per block of 2425μm x 1525μm needed to fit the design in.

³ Price = per block of 1875μm x 1875μm needed to fit the design in. Adding two blocks together to one block is possible.

* UMC 0.18μm mini@sic rules

When the standard block of 5mm x 5mm is divided into 9 regular square sub-blocks, customers participating in the mini@sic program can submit one sub-block or multiple sub-blocks, depending on the size of their design:

single sub-block: design may not be larger than 1525μm x 1525μm
2 sub-blocks: design may not be larger than 3240μm x 1525μm
3 sub-blocks: design may not be larger than 4960μm x 1525μm
4 sub-blocks: design may not be larger than 3240μm x 3240μm
6 sub-blocks: design may not be larger than 4960μm x 3240μm

Final price = number of sub-blocks needed to fit in the design * sub-block price.

** UMC 0.11μm mini@sic rules

single sub-block: design may not be larger than 2425μm x 1525μm
2 sub blocks: design may not be larger than 2425μm x 3140μm

*** UMC 65nm mini@sic rules

For the mini@sic program, customers can submit one sub-block or multiple sub-blocks, depending on the size of their design:

single sub-block: design may not be larger than 1875μm x 1875μm
2 sub-blocks: design may not be larger than 3950μm x 1875μm

X-FAB MPW	Jan	Feb	Mar	Apr	May	Jun	Jul	Aug	Sep	Oct	Nov	Dec
XH018 0.18µ HV NVM CMOS E-FLASH	3			25			11			24		19
XT018 0.18µ HV SOI CMOS			21			13		15			7
XS018 0.18µ OPTO *		28							5
XP018 0.18µ NVM CMOS *		7			30					3
XH035 0.35µ HV CMOS	10			29				5			4
XR013 0.13µ RF SOI CMOS *		22			23			22			7
XMB10 MEMS									14

Important notes: Dates are GDS submission deadlines. Registration should be done at least 2 weeks in advance.

* In case of cancellation, there is a possibility to order these technologies by MLM.

Please take a look at additional technology options:

X-FAB MPW Pricelist	Standard EUR / mm²	Discounted EUR / mm²
X-FAB XH018 0.18μ HV NVM CMOS E-FLASH (MET3, MET4, METMID, MET-THK)	1,605	1,525
X-FAB XT018 0.18μ HV SOI CMOS (MET3, MET4, METMID, METTHK)	1,635	1,555
X-FAB XS018 0.18μ OPTO (MET3, MET4, MET5, METMID)	1,375	1,310
X-FAB XP018 0.18μ NVM CMOS (MET3, MET4, METMID, METTHK)	1,415	1,345
X-FAB XH035 0.35μ HV CMOS (MET4)	1,035	985
X-FAB XR013 0.13μ RF SOI CMOS (METRB, METBQ)	1,830	1,745
X-FAB XR013 0.13μ RF SOI CMOS (METTHK1, METRB, METRQ)	2,280	2,165
XMB10 MEMS	1,050 ¹	980 ¹

Important notes:

Price = area (mm²) * price/mm² with min. fabrication cost equivalent to 10mm².
Area will be rounded upwards to the next mm² (for instance, 12.24mm² will be charged as 13mm²).
Backgrinding (necessary for packaging) is not always possible and an additional cost might apply.

Delivery of 50 dies is included. Purchasing additional dies is not always possible and an additional cost may apply.

¹ Delivery of 5 dies is included. Additional dies can be purchased for 10EUR/die (50 dies maximum).

X-FAB mini@sic		Jan	Feb	Mar	Apr	May	Jun	Jul	Aug	Sep	Oct	Nov	Dec
XH018 0.18µ HV NVM CMOS E-FLASH					25						24
XT018 0.18µ HV SOI CMOS				21								7

Important notes: Dates are GDS submission deadlines. Registration should be done at least 2 weeks in advance.

Please take a look at additional technology options:

X-FAB mini@sic Pricelist		Standard EUR / block	Discounted EUR / block
X-FAB XH018 0.18μ HV NVM CMOS E-FLASH (MET3, MET4, METMID, MET-THK)		4,065	3,750
X-FAB XT018 0.18μ HV SOI CMOS (MET3, MET4, METMID, METTHK)		4,145	3,825

Important notes:

Price = per block of 1520μm x 1520μm needed to fit the design in. Adding two blocks together to one block is possible.
Backgrinding (necessary for packaging) is not always possible and an additional cost might apply.

Delivery of 50 dies is included. Purchasing additional dies is not always possible and an additional cost may apply.

CORNERSTONE MPW	Jan	Feb	Mar	Jun	Jul	Sep	Oct	Dec
CORNERSTONE Si-Photonics: 220 nm SOI passives			25			30
CORNERSTONE Si-Photonics: 220 nm SOI actives							28
CORNERSTONE Si-Photonics: 340 nm SOI passives	7
CORNERSTONE Si-Photonics: 500 nm SOI passives				24
CORNERSTONE SiN-Photonics	7			24				23
CORNERSTONE Si-Photonics: Suspended-Si		25			29

Important notes: Dates are GDS submission deadlines. Registration should be done at least 4 weeks in advance.

CORNERSTONE MPW Pricelist	Standard EUR	Discounted EUR
Half block – Passives only, all SOI platforms (5.5mm x 4.9mm)	6,200	5,875
Full block – Passives only, all SOI platforms (11.47mm x 4.9mm)	9,300	8,875
Half block – Passives with heaters, all SOI platforms (5.5mm x 4.9mm)	11,700	11,125
Full block – Passives with heaters, all SOI platforms (11.47mm x 4.9mm)	17,100	16,250
Half block – Actives, 220nm SOI platform (5.5mm x 4.9mm)	28,250	26,875
Full block – Actives, 220nm SOI platform (11.47mm x 4.9mm)	49,250	46,875
SiN full block – SiN platform with heaters (11.47mm x 15.45mm)	14,200	13,500
SiN full block – SiN platform, passive (11.47mm x 15.45mm)	7,350	7,000
Suspended-Si full block (11.47mm x 4.9mm)	6,850	6,500
Suspended-Si half block (5.5mm x 4.9mm)	5,000	4,750
Extra Options
Extra set of blocks – Passives (10 samples)	+2,200	+2,200
Extra set of blocks – Passives with heaters (10 samples)	+3,000	+3,000
Extra set of blocks – Actives (10 samples)	+5,000	+5,000

Important notes:

Standard number of samples for all platforms is 10. If more prototypes are needed, please see Extra Options in the table above.

imec MPW	Mar	May	Jun	Oct
imec Si-Photonics Passives+ ¹			1
imec Si-Photonics iSiPP50G	9			5
imec SiN-Photonics BioPIX 300		3		31
imec GaN-IC on SOI 200V			22
imec GaN-IC on SOI 650V				19

Important notes: Dates indicate deadlines for both Registration and submission of the first version of the GDS file.

¹ The Q4 2022’s Silicon Photonics Passives+ run will be shifted to January 2023

imec MPW Pricelist Si-Photonics Passives+ ^{1, 2}	Standard EUR	Discounted EUR
Half block – horizontal (5.15mm x 2.5mm) or vertical (2.5mm x 5.15mm)	6,100	5,800
1 block (5.15mm x 5.15mm)	11,600	11,000
2 blocks – horizontal (10.45mm x 5.15mm) or vertical (5.15mm x 10.45mm)	20,600	19,600
Larger sizes	Please, contact epsiphot@imec.be
Extra Options
Extra set of half block chips (10 samples)	+2,000	+2,000
Extra set of chips (1 block or larger; 20 samples)	+2,000	+2,000
Si-Photonics iSiPP50G ²
Quarter block (2.5mm x 2.5mm)	10,000	9,500
Half block – horizontal (5.15mm x 2.5mm) or vertical (2.5mm x 5.15mm)	20,000	19,000
1 block (5.15mm x 5.15mm)	40,000	38,000
2 blocks – horizontal (10.45mm x 5.15mm) or vertical (5.15mm x 10.45mm)	80,000	76,000
4 blocks (10.45mm x 10.45mm)	150,000	142,500
Larger sizes	Please, contact epsiphot@imec.be
Extra Options
Extra set of quarter block chips (10 samples)	+2,000	+2,000
Extra set of half block chips (10 samples)	+2,000	+2,000
Extra set of chips (1 block or larger; 20 samples)	+2,000	+2,000

Important notes:

¹ Imec Si-Photonics Passives technology is replaced by imec Si-Photonics Passives+ technology in 2019. Imec Si-photonics passives+ allows for metal heaters and edge-couplers, but its introduction also implies a few other changes to the offer. Existing users, please be cautious.

² Number of prototypes in standard order depends on design size: 20 for 1 block or larger, 10 for half block or smaller.
Due to the nature of MPW logistics, more chips than ordered may sometimes be shipped.

imec MPW Pricelist SiN-Photonics BioPIX 300 and 150	Standard EUR	Discounted EUR
1 block (5.30mm x 4.75mm)	23,000	21,850
2 blocks – horizontal (10.75mm x 4.75mm)	46,000	43,700
2 blocks – vertical (5.30mm x 9.65mm)	46,000	43,700
4 blocks (10.75mm x 9.65mm)	92,000	87,400
Larger sizes	Please, contact sinmpw@imec-int.com
Extra Options
Extra set of chips (20 samples)	+1,000	+1,000

Important notes:

Number of prototypes in base order: 20 samples, for each design block registration irrespective of the block size.
Due to the nature of MPW logistics, more chips than ordered may sometimes be shipped.

imec MPW Pricelist GaN-IC on SOI 200V and 650V	Standard EUR	Discounted EUR
Half block (2.5mm x 5.18mm) *	22,000	20,240
Standard block (5.18mm x 5.18mm)	44,000	40,480
Double block (10.54mm x 5.18mm)	88,000	80,960
Extra Options
Extra set of chips (40 samples)	+5,000	+5,000
Sub-dicing **	+1,000	+1,000

Important notes: Regular number of samples is 40 .
Due to the nature of MPW logistics, more chips than ordered may sometimes be shipped.
* This option is only available to academic institutions.

** Per additional dicing lane, following MPW templates only. Sub-dicing options must be approved by the technical team. Please contact ganmpw@imec-int.com in advance to evaluate your request.

LioniX MPW	Mar	Jun	Jul	Nov
LNX SiN-Photonics TriPleX VIS	31
LNX SiN-Photonics TriPleX 1550	31		31	15
LNX SiN-Photonics TriPleX 850		7

Important notes:

Dates are GDS submission deadlines. For registration dates and other details, please contact europratice.gateway@tyndall.ie

TBD * – The exact dates in June for TriPleX VIS and in September for TriPleX 850 are to be defined.

LioniX MPW Pricelist SiN-Photonics TriPleX		Standard EUR	Discounted EUR
4 samples of 10mm x 10mm		16,000	8,500¹
4 samples of 10mm x 20mm		24,000	12,500 ¹

Important notes:

For academic customers, the discount on the device manufacturing is offered on the condition that LioniX International will be co-author or acknowledged in the publications related to these devices.

MEMSCAP MPW	Jan	Feb	Mar	May	Jul	Sep	Nov
PolyMUMPs		15			26
SOIMUMPS			1		5		2
PiezoMUMPS	11			3		6

Important notes: Dates indicate deadlines for both Registration and submission of the first version of the GDS file.

MEMSCAP MPW Pricelist		Standard EUR / block	Discounted EUR / block
PolyMUMPs (10mm x 10mm), SOIMUMPs (11 mm x 11mm), PiezoMUMPs (11mm x 11mm)		4,400	4,200

Fraunhofer IZM		Jan	Feb	Mar	Apr	May	Jun	Jul	Aug	Sep	Oct	Nov	Dec
Fan-Out Wafer-Level Packaging (FOWLP)					11*							18**

Important notes:

* FOWLP package design according Design Rules IZM (“Layout”): until April 11, 2022

Chips to be processed including 5 to 10 set-up chips: until May 27, 2022

** FOWLP package design according Design Rules IZM (“Layout”): until November 18, 2022

Chips to be processed including 5 to 10 set-up chips: until January 06, 2023

Fraunhofer IZM Pricelist	Standard EUR	Discount EUR
Up to 30 Chips/Packages (other prices on request)	14,400	12,000
Up to 50 Chips/Packages	20,400	17,000
Up to 100 Chips/Packages	27,600	23,000
Each additional DRC per Design update	900	750

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