EM Microelectronic

Since 2020, EUROPRACTICE starts to provide access to the EMALP18 logic technology of EM Microelectronic.

EM Microelectronic 0.18µm EMALP18 logic
Technology characteristics
Met. layers: 4/5. Option B -4ML or Option M -5ML
Minimum Gate length: 180nm [drawn]
Dual Gate Oxides: 3.0nm ThinGOX [1.98V max] and 6.5nm DualGOX [3.63V max]
FEOL isolation: Non Epi or p-Epi substrate [16-24Ω.cm], STI [Shallow trench isolation]
Supply voltage: 1.8V or 3.3V
Special features
EKV models with parameters for near/sub Vth operations
Digital cell library optimized for Low Power/Low Voltage
I/O pads library with low leakage ESD protections
Application area
Ultra-Low Power, Ultra-Low Voltage
Analog Designs (low leakage, low noise, pairing)
Mixed signal (100kGates/mm2)
Low current (nA bias), Low voltage (down to 0.4V)
Design kits version
2.1 (May-20)
Frontend Backend tools
Cadence IC 6.1.7
Simulation tools
Spectre (Cadence), Incisive (Cadence)
Verification tools
PVS (Cadence)
Parasitics extraction tools
QRC (Cadence)
Place route tools
Innovus (Cadence)
Turnaround Time
10-12 weeks from MPW run deadline to packaged parts